View SAA7182AWP_100697.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
DATA SHEET
SAA7182A; SAA7183A Digital Video Encoder (EURO-DENC2)
Preliminary specification Supersedes data of 1996 Sep 11 File under Integrated Circuits, IC22 1996 Oct 02
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
FEATURES * Monolithic CMOS 3.3 V device with 5 V input stages * Digital PAL/NTSC/SECAM encoder * System pixel frequency 13.5 MHz * Accepts MPEG decoded data on 8-bit wide input port. Input data format Cb, Y, Cr etc. "(CCIR 656)" or Y and Cb, Cr on 16 lines * Three DACs for CVBS, Y and C operating at 27 MHz with 10 bit resolution * Three DACs for RGB operating at 27 MHz with 9 bit resolution, RGB sync on CVBS and Y * Analog multiplexing between internal RGB and external RGB on-chip * CVBS, Y, C and RGB output simultaneously * Closed captioning and teletext encoding including sequencer and filter * Line 23 wide screen signalling encoding * On-chip Cr, Y, Cb to RGB dematrix, including gain adjustment for Y and Cr, Cb, optionally to be by-passed for Cr, Y, Cb output on RGB DACs * Fast I2C-bus control port (400 kHz) * Encoder can be master or slave * Programmable horizontal and vertical input synchronization phase * Programmable horizontal sync output phase * Internal Colour Bar Generator (CBG) * Overlay with Look-Up Tables (LUTs) 8 x 3 bytes * Macrovision Pay-per-View copy protection system as option, also used for RGB output.
SAA7182A; SAA7183A
This applies to SAA7183A only. The device is protected by USA patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anti-copy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductor sales office for more information * Controlled rise/fall times of output syncs and blanking * Down-mode of DACs * PQFP80 or PLCC84 package. GENERAL DESCRIPTION The SAA7182A; SAA7183A encodes digital YUV video data to an NTSC, PAL, SECAM CVBS or S-Video signal and also RGB. Optionally, the YUV to RGB dematrix can be by-passed providing the digital-to-analog converted Cb, Y, Cr signals instead of RGB. The circuit accepts CCIR compatible YUV data with 720 active pixels per line in 4 : 2 : 2 multiplexed formats, for example MPEG decoded data. It includes a sync/clock generator and on-chip Digital-to-Analog Converters (DACs). The circuit is compatible to the DIG-TV2 chip family.
ORDERING INFORMATION TYPE NUMBER SAA7182AWP; SAA7183AWP PACKAGE NAME PLCC84 QFP80 DESCRIPTION plastic leaded chip carrier; 84 leads plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm VERSION SOT189-2 SOT318-2
1996 Oct 02
2
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
QUICK REFERENCE DATA SYMBOL VDDA3 VDDD3 VDDD5 IDDA IDDD3 IDDD5 Vi Vo(p-p) RL ILE DLE Tamb PARAMETER 3.3 V analog supply voltage 3.3 V digital supply voltage 5 V digital supply voltage analog supply current 3.3 V digital supply current 5 V digital supply current input signal voltage levels
SAA7182A; SAA7183A
MIN. 3.1 3.0 4.75 - - -
TYP. 3.3 3.3 5.0 - - - 1.4 - - - -
MAX. 3.5 3.6 5.25 110 80 10 - 300 2 1 +70
UNIT V V V mA mA mA V LSB LSB C
TTL compatible
analog output signal voltages Y, C, CVBS and RGB without load - (peak-to-peak value) load resistance LF integral linearity error LF differential linearity error operating ambient temperature 75 - - 0
1996 Oct 02
3
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
BLOCK DIAGRAM
SAA7182A; SAA7183A
RTCI
handbook, full pagewidth
RCV1
TTXRQ XTALO CREF
LLC VDDA4 to VDDA9 TESTB 75 63, 64, 68, 70, 72, 74
RESET SDA SCL SA CDIR 1 84 83 4 I2C-bus control I2C-BUS INTERFACE 8 I2C-bus control 8 37
RCV2
XTALI
50 35 36 20 47 45 44 48
SECAM PROCESSOR
SYNC CLOCK I2C-bus control 73 OUTPUT INTERFACE D A 71 69 CVBS Y CHROMA VSSA1 to VSSA3 TESTC SELI RI RED GREEN BLUE
DP0 to DP7 MP7 to MP0 OVL2 to OVL0 KEY
10 to 13 16 to 19 8 25 to 28 31 to 34 8 6 to 8 3 9
DbDr Y Y ENCODER CbCr C
clock and timing
8
DATA MANAGER
8 I2C-bus control
I2C-bus control
internal control bus
8
I2C-bus control
52, 67, 76 53 65
TTX
21 3
SAA7182A SAA7183A
Y CbCr
8
I2C-bus control D A
62 61
RGB PROCESSOR
58 55
3, 15, 24, 30, 39, 42, 51, 79, 81 VSSD1 to VSSD9
5, 14, 22, 29, 38, 46, 49, 80, 82 VDDD1 to VDDD9
2, 23, 40, 41, 43, 66 n.c.
78 SP
77 AP
59 GI
56
54, 57, 60 VDDA1 to VDDA3
MGD668
BI
Fig.1 Block diagram; PLCC84.
1996 Oct 02
4
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
RTCI
handbook, full pagewidth
RCV1
TTXRQ XTALO CREF
LLC VDDA4 to VDDA9 TESTB 63 52, 53, 56, 58, 60, 62
RESET SDA SCL SA CDIR 73 72 71 75 I2C-bus control I2C-BUS INTERFACE 8 I2C-bus control 8 27
RCV2
XTALI
38 25 26 11 35 33 32 36
SECAM PROCESSOR
SYNC CLOCK I2C-bus control 61 OUTPUT INTERFACE D A 59 57 CVBS Y CHROMA VSSA1 to VSSA3 TESTC SELI RI RED GREEN BLUE
DP0 to DP7 MP7 to MP0 OVL2 to OVL0 KEY
1 to 4 7 to 10 8 15 to 18 21 to 24 8 77 to 79 3 80
DbDr Y Y ENCODER CbCr C
clock and timing
8
DATA MANAGER
8 I2C-bus control
I2C-bus control
internal control bus
8
I2C-bus control
41, 55, 64 42 54
TTX
12 3
SAA7182A SAA7183A
Y CbCr
8
I2C-bus control D A
51 50
RGB PROCESSOR
47 44
6, 14, 20, 29, 31, 39, 67, 69, 74 VSSD1 to VSSD9
5, 13, 19, 28, 34, 37, 68, 70, 76 VDDD1 to VDDD9
30, 40 n.c.
66 SP
65 AP
48 GI
45
43, 46, 49 VDDA1 to VDDA3
MGD670
BI
Fig.2 Block diagram; QFP80.
1996 Oct 02
5
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
PINNING PIN SYMBOL PLCC84 RESET n.c. VSSD1 SA VDDD1 OVL2 OVL1 OVL0 KEY DP0 DP1 DP2 DP3 VDDD2 VSSD2 DP4 DP5 DP6 DP7 TTXRQ TTX VDDD3 n.c. VSSD3 MP7 MP6 MP5 MP4 VDDD4 VSSD4 MP3 MP2 MP1 MP0 RCV1 RCV2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 QFP80 73 - 6 75 13 77 78 79 80 1 2 3 4 5 14 7 8 9 10 11 12 28 - 20 15 16 17 18 19 29 21 22 23 24 25 26 digital supply voltage 4 (5 V) digital ground 4 digital supply voltage 2 (5 V) digital ground 2
SAA7182A; SAA7183A
DESCRIPTION Reset input, active LOW. After reset is applied, all digital I/Os are in input mode. The I2C-bus receiver waits for the START condition. not connected digital ground 1 The I2C-bus slave address select input pin. LOW: slave address = 88H, HIGH = 8CH. digital supply voltage 1 (3.3 V) 3-bit overlay data input. This is the index for the internal look-up table. Key input for OVL. When HIGH it selects OVL input. Lower 4 bits of the data port. Input for multiplexed Cb, Cr data if 16 line input mode is used.
Upper 4 bits of the data port. Input for multiplexed Cb, Cr data if 16 line input mode is used. Teletext request output, indicating when bit stream is valid. Teletext bit stream input. digital supply voltage 3 (3.3 V) not connected digital ground 1 Upper 4 bits of MPEG port. It is an input for "CCIR 656" style multiplexed Cb, Y, Cr data, or for Y data only, if 16 line input mode is used.
Lower 4 bits of MPEG port. It is an input for "CCIR 656" style multiplexed Cb, Y, Cr data, or for Y data only, if 16 line input mode is used. Raster Control 1 for video port. This pin receives/provides a VS/FS/FSEQ signal. Raster Control 2 for video port. This pin provides an HS pulse of programmable length or receives an HS pulse. 6
1996 Oct 02
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
PIN SYMBOL PLCC84 RTCI 37 QFP80 27 Real Time Control input. If the LLC clock is provided by an SAA7111 or SAA7151B, RTCI should be connected to the RTCO pin of the respective decoder to improve the signal quality. digital supply voltage 5 (3.3 V) digital ground 5 not connected not connected digital ground 6 for oscillator not connected Crystal oscillator input (from crystal). If the oscillator is not used, this pin should be connected to ground. Crystal oscillator output (to crystal). digital supply voltage 6 for oscillator (3.3 V) Clock Reference signal. This is the clock qualifier for DIG-TV2 compatible signals. Line-Locked Clock. This is the 27 MHz master clock for the encoder. The I/O direction is set by the CDIR pin. digital supply voltage 7 (5 V) Clock direction. If CDIR input is HIGH, the circuit receives a clock and optional CREF signal, otherwise if CDIR is LOW, CREF and LLC are generated by the internal crystal oscillator. digital ground 7 Analog ground 1 for the DACs. Analog test pin. Leave open-circuit for normal operation. Analog supply voltage 1 for the RGB DACs (3.3 V). Analog output of the BLUE component. Analog input that can be switched to BLUE when SELI = HIGH. Analog supply voltage 2 for RGB DACs (3.3 V). Analog output of GREEN component. Analog input that can be switched to GREEN when SELI = HIGH. Analog supply voltage 3 for RGB DACs (3.3 V). Analog output of RED component. Analog input that can be switched to RED when SELI = HIGH. Analog supply voltage 4 for DACs (3.3 V). Analog supply voltage 5 for DACs (3.3 V). Select analog input. Digital-to-analog converted RGB output when SELI = LOW; RI, GI and BI output when SELI = HIGH. not connected Analog ground 2 for the DACs. Analog supply voltage 6 for DACs (3.3 V). Analog output of the chrominance signal. Analog supply voltage 7 for the Y/C/CVBS DACs (3.3 V). 7 DESCRIPTION
VDDD5 VSSD5 n.c. n.c. VSSD6 n.c. XTALI XTALO VDDD6 CREF LLC VDDD7 CDIR
38 39 40 41 42 43 44 45 46 47 48 49 50
68 39 40 - 31 30 32 33 34 35 36 37 38
VSSD7 VSSA1 TESTC VDDA1 BLUE BI VDDA2 GREEN GI VDDA3 RED RI VDDA4 VDDA5 SELI n.c. VSSA2 VDDA6 CHROMA VDDA7 1996 Oct 02
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
67 41 42 43 44 45 46 47 48 49 50 51 52 53 54 - 55 56 57 58
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
PIN SYMBOL PLCC84 Y VDDA8 CVBS VDDA9 TESTB VSSA3 AP SP VSSD8 VDDD8 VSSD9 VDDD9 SCL SDA 71 72 73 74 75 76 77 78 79 80 81 82 83 84 QFP80 59 60 61 62 63 64 65 66 69 76 74 70 71 72 Analog output of VBS signal. Analog supply voltage 8 for the Y/C/CVBS DACs. Analog output of the CVBS signal. Analog supply voltage 9 for the Y/C/CVBS DACs. Analog test pin. Leave open-circuit for normal operation. Analog ground 3 for the DACs. Test pin. Connected to digital ground for normal operation. Test pin. Connected to digital ground for normal operation. digital ground 8 digital supply voltage 8 (3.3 V) digital ground 9 digital supply voltage 9 (5 V) I2C-bus serial clock input. I2C-bus serial data input/output. DESCRIPTION
1996 Oct 02
8
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
5 VDDD1
82 VDDD9
80 VDDD8
1 RESET
3 VSSD1
81 VSSD9
79 VSSD8
76 VSSA3
8 OVL0
7 OVL1
6 OVL2
handbook, full pagewidth
DP2 12 DP3 13 VDDD2 14 VSSD2 15 DP4 16 DP5 17 DP6 18 DP7 19 TTXRQ 20 TTX 21 VDDD3 22 n.c. 23 VSSD3 24 MP7 25 MP6 26 MP5 27 MP4 28 VDDD4 29 VSSD4 30 MP3 31 MP2 32 MP1 33 MP0 34 RCV1 35 RCV2 36 RTCI 37 VDDD5 38 VSSD5 39 n.c. 40 n.c. 41 VSSD6 42 n.c. 43 XTALI 44 XTALO 45 VDDD6 46 CREF 47 LLC 48 VDDD7 49 CDIR 50 VSSD7 51 VSSA1 52 TESTC 53
75 TESTB 74 VDDA9 73 CVBS 72 VDDA8 71 Y 70 VDDA7 69 CHROMA 68 VDDA6 67 VSSA2 66 n.c. 65 SELI 64 VDDA5 63 VDDA4 62 RI 61 RED 60 VDDA3 59 GI 58 GREEN 57 VDDA2 56 BI 55 BLUE 54 VDDA1
84 SDA
11 DP1
10 DP0
9 KEY
83 SCL
2 n.c.
4 SA
78 SP
SAA7182A SAA7183A
77 AP
MGD669
Fig.3 Pin configuration; PLCC84.
1996 Oct 02
9
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
76 VDDD8
70 VDDD9
68 VDDD5
73 RESET
74 VSSD9
69 VSSD8
67 VSSD7
79 OVL0
78 OVL1
77 OVL2
72 SDA
80 KEY
71 SCL
75 SA
66 SP
handbook, full pagewidth
DP0 1 DP1 2 DP2 3 DP3 4 VDDD2 5 VSSD1 6 DP4 7 DP5 8 DP6 9 DP7 10 TTXRQ 11 TTX 12 VDDD1 13 VSSD2 14 MP7 15 MP6 16 MP5 17 MP4 18 VDDD4 19 VSSD3 20 MP3 21 MP2 22 MP1 23 MP0 24 RCV1 25 RCV2 26 RTCI 27 VDDD3 28 VSSD4 29 n.c. 30 VSSD6 31 XTALI 32 XTALO 33 VDDD6 34 CREF 35 LLC 36 VDDD7 37 CDIR 38 VSSD5 39 n.c. 40
65 AP 64 VSSA3 63 TESTB 62 VDDA9 61 CVBS 60 VDDA8 59 Y 58 VDDA7 57 CHROMA 56 VDDA6 55 VSSA2 54 SELI 53 VDDA5 52 VDDA4 51 RI 50 RED 49 VDDA3 48 GI 47 GREEN 46 VDDA2 45 BI 44 BLUE 43 VDDA1 42 TESTC 41 VSSA1
MGD671
SAA7182A SAA7183A
Fig.4 Pin configuration; QFP80.
1996 Oct 02
10
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
FUNCTIONAL DESCRIPTION The digital video encoder (EURO-DENC2) encodes digital luminance and colour difference signals into analog CVBS and simultaneously S-Video signals. NTSC-M, PAL B/G, SECAM standards and sub-standards are supported. Both interlaced and non-interlaced operation is possible for all standards. In addition, the de-matrixed Y, Cb, and Cr input is available on three separate analog outputs as RED, GREEN and BLUE. Under software control the dematrix can be by-passed to output digital-to-analog converted Cr, Y, and Cb signals on RGB outputs. Separate digital gain adjustment for luminance and colour difference signals is available. Analog on-chip multiplexing between internal digital-to-analog converted RGB and external RI, GI and BI signals is also supported. The basic encoder function consists of subcarrier generation, colour modulation and insertion of synchronization signals. Luminance and chrominance signals are filtered in accordance with the standard requirements of "RS-170-A" and "CCIR 624". For ease of analog post filtering the signals are twice oversampled with respect to the pixel clock before digital-to-analog conversion. For total filter transfer characteristics see Figs 5, 6, 7, 8, 9 and 10. The DACs for Y, C, and CVBS are realized with full 10-bit resolution, DACs for RGB are with 9-bit resolution. The MPEG port (MP) accept 8 line multiplexed Cb, Y, Cr data. The 8-bit multiplexed Cb-Y-Cr formats are "CCIR 656" (D1 format) compatible, but the SAV and EAV codes can be decoded optionally, when the device is to operate in slave mode. Alternatively, 8-bits Y on MP port and 8-bit multiplexed Cb, Cr on DP port can be chosen as input. A crystal-stable master clock (LLC) of 27 MHz, which is twice the CCIR line-locked pixel clock of 13.5 MHz, needs to be supplied externally. Optionally, a crystal oscillator input/output pair of pins and an on-chip clock driver is provided. It is also possible to connect a Philips Digital Video Decoder (SAA7111 or SAA7151B) in conjunction with a CREF clock qualifier to EURO-DENC2. Via the RTCI pin, connected to RTCO of a decoder, information concerning
SAA7182A; SAA7183A
actual subcarrier, PAL-ID, and if connected to SAA7111, definite subcarrier phase can be inserted. The EURO-DENC2 synthesizes all necessary internal signals, colour subcarrier frequency, and synchronization signals, from that clock. European teletext encoding is supported if an appropriate teletext bitstream is applied to the TTX pin. Wide screen signalling data can be loaded via the I2C-bus, and is inserted into line 23 for standards using 50 Hz field rate. The IC also contains Closed Caption and Extended Data Services Encoding (Line 21), and supports anti-taping signal generation in accordance with Macrovision; it also supports overlay via KEY and three control bits by a 24 x 8 LUT. A number of possibilities are provided for setting different video parameters such as: Black and blanking level control Colour subcarrier frequency Variable burst amplitude etc. During reset (RESET = LOW) and after reset is released, all digital I/O stages are set to input mode. A reset forces the I2C-bus interface to abort any running bus transfer and sets register 3A to 03H, register 61 to 06H and registers 6BH and 6EH to 00H. All other control registers are not influenced by a reset. Data manager In the data manager, real time arbitration on the data stream to be encoded is performed. Depending on the polarity of pin KEY, the MP input (or MP/DP input) or OVL input are selected to be encoded to CVBS and Y/C signals, and output as RGB. KEY controls OVL entries of a programmable LUT for encoded signals and for RGB output. The common KEY switching signal can be disabled by software for the signals to be encoded (Y, C and CVBS), such that OVL will appear on RGB outputs, but not on Y, C and CVBS. OVL input under control of KEY can be also used to insert decoded teletext information or other on-screen data. Optionally, the OVL colour LUTs located in this block, can be read out in a pre-defined sequence (8 steps per active video line), achieving, for example, a colour bar test pattern generator without need for an external data source. The colour bar function is only under software control.
1996 Oct 02
11
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
Encoder VIDEO PATH The encoder generates out of Y, U and V baseband signals luminance and colour subcarrier output signals, suitable for use as CVBS or separate Y and C signals. Luminance is modified in gain and in offset (latter programmable in a certain range to enable different black level set-ups). After having been inserted a fixed synchronization level, in accordance with standard composite synchronization schemes, and blanking level, programmable also in a certain range to allow for manipulations with Macrovision anti-taping, additional insertion of AGC super-white pulses, programmable in height, is supported. In order to enable easy analog post filtering, luminance is interpolated from 13.5 MHz data rate to 27 MHz data rate, providing luminance in 10-bit resolution. This filter is also used to define smoothed transients for synchronization pulses and blanking period. For transfer characteristic of the luminance interpolation filter see Figs 7 and 8. Chrominance is modified in gain (programmable separately for U and V), standard dependent burst is inserted, before baseband colour signals are interpolated from 6.75 MHz data rate to 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be made use of for Y and C output. For transfer characteristics of the chrominance interpolation filter see Figs 5 and 6. The amplitude of inserted burst is programmable in a certain range, suitable for standard signals and for special effects. Behind the succeeding quadrature modulator, colour in 10-bit resolution is provided on subcarrier. The numeric ratio between Y and C outputs is in accordance with set standards. TELETEXT INSERTION AND ENCODING Pin TTX receives a teletext bitstream sampled at the LLC clock, each teletext bit is carried by four or three LLC samples. Phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines. TTXRQ provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines selectable independently for both fields. The internal insertion window for text is set to 360 teletext bits including clock run-in bits. For protocol and timing see Fig.19. 1996 Oct 02 12
SAA7182A; SAA7183A
CLOSED CAPTION ENCODER Using this circuit, data in accordance with the specification of Closed Caption or Extended Data Service, delivered by the control interface, can be encoded (Line 21). Two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. The actual line number where data is to be encoded in, can be modified in a certain range. Data clock frequency is in accordance with definition for NTSC-M standard 32 times horizontal line frequency. Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE. It is also possible to encode Closed Caption Data for 50 Hz field frequencies at 32 times horizontal line frequency. ANTI-TAPING (SAA7183A ONLY) For more information contact your nearest Philips Semiconductors sales office. RGB processor This block contains a dematrix in order to produce RED, GREEN and BLUE signals to be fed to a SCART plug. Before Y, Cb and Cr signals are de-matrixed, individual gain adjustment for Y and colour difference signals and 2 times oversampling for luminance and 4 times oversampling for colour difference signals is performed. For transfer curves of luminance and colour difference components of RGB see Figs 9 and 10. SECAM processor SECAM specific pre-processing is achieved in this block by a pre-emphasis of colour difference signals (for gain and phase see Figs 11 and 12). A baseband frequency modulator with a reference frequency shifted from 4.286 MHz to DC carries out SECAM modulation in accordance with appropriate standard or optionally wide clipping limits. After the HF pre-emphasis, also applied on a DC reference carrier (anti-Cloche filter; see Figs 13 and 14), line-by-line sequential carriers with black reference of 4.25 MHz (Db) and 4.40625 MHz (Dr) are generated using specified values for FSC programming bytes. Alternating phase reset in accordance with SECAM standard is carried out automatically. During vertical blanking the so-called bottle pulses are not provided.
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
Output interface/DACs In the output interface encoded both Y and C signals are converted from digital-to-analog in 10-bit resolution. Y and C signals are also combined to a 10-bit CVBS signal. The CVBS output occurs with the same processing delay as the Y and C outputs. Absolute amplitudes at the input of the DAC for CVBS is reduced by 1516 with respect to Y and C DACs to make maximum use of conversion ranges. RED, GREEN and BLUE signals are also converted from digital-to-analog, each providing a 9-bit resolution. It is also possible to feed through three external analog RGB signals at pins RI, BI and GI when pin SELI = HIGH Outputs of the DACs can be set together in two groups via software control to minimum output voltage for either purpose. Synchronization Synchronization of the EURO-DENC2 is able to operate in two modes; slave mode and master mode. In the slave mode, the circuit accepts synchronization pulses at the bidirectional RCV1 port. The timing and trigger behaviour related to RCV1 can be influenced by programming the polarity and on-chip delay of RCV1. Active slope of RCV1 defines the vertical phase and optionally the odd/even and colour frame phase to be initialized, it can be also used to set the horizontal phase. If the horizontal phase is not to be influenced by RCV1, a horizontal pulse needs to be supplied at the RCV2 pin. Timing and trigger behaviour can also be influenced for RCV2. If there are missing pulses at RCV1 and/or RCV2, the time base of EURO-DENC2 runs free, thus an arbitrary number of synchronization slopes may miss, but no additional pulses (with the incorrect phase) must occur. If the vertical and horizontal phase is derived from RCV1, RCV2 can be used for horizontal or composite blanking input or output. Alternatively, the device can be triggered by auxiliary codes in a CCIR 656 data stream at the MP port In the master mode, the time base of the circuit continuously runs free. On the RCV1 port, the IC can output:
SAA7182A; SAA7183A
* A Vertical Sync signal (VS) with 3 or 2.5 lines duration, or; * An ODD/EVEN signal which is LOW in odd fields, or; * A field sequence signal (FSEQ) which is HIGH in the first of 4, 8, 12 fields respectively. On the RCV2 port, the IC can provide a horizontal pulse with programmable start and stop phase; this pulse can be inhibited in the vertical blanking period to build up, for example, a composite blanking signal. The polarity of both RCV1 and RCV2 is selectable by software control. The length of a field and the start and end of its active part can be programmed. The active part of a field always starts at the beginning of a line. I2C-bus interface The I2C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are write only, except one readable status byte. Two I2C-bus slave addresses are selected: 88H: LOW at pin SA 8CH: HIGH at pin SA. Input levels and formats EURO-DENC2 expects digital Y, Cb, Cr data with levels (digital codes) in accordance with "CCIR 601". For C and CVBS outputs, deviating amplitudes of the colour difference signals can be compensated by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up. For RGB outputs variable amplification of the Y, Cb and Cr components is provided, enabling adjustment of contrast and colour saturation in certain range. Reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation.
1996 Oct 02
13
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
Table 1
SAA7182A; SAA7183A
"CCIR 601" signal component levels
SIGNALS(1)
COLOUR Y White Yellow Cyan Green Magenta Red Blue Black Notes 1. Transformation: a) R = Y + 1.3707 x (Cr - 128) b) G = Y - 0.3365 x (Cb - 128) - 0.6982 x (Cr - 128) c) B = Y + 1.7324 x (Cb - 128). 235 210 170 145 106 81 41 16 Cb 128 16 166 54 202 90 240 128 Cr 128 146 16 34 222 240 110 128
R(2) 235 235 16 16 235 235 16 16
G(2) 235 235 235 235 16 16 16 16
B(2) 235 16 235 16 235 16 235 16
2. Representation of R, G and B (or Cr, Y and Cb) at the output is 9 bits at 27 MHz. Table 2 8-bit multiplexed format (similar to "CCIR 601") BITS TIME 0 Sample Luminance pixel number Colour pixel number Table 3 16-bit multiplexed format (DTV2 format) BITS TIME 0 Sample Y line Sample UV line Luminance pixel number Colour pixel number Y0 Cb0 0 0 1 2 Y1 Cr0 1 3 4 Y2 Cb2 2 2 5 6 Y3 Cr2 3 7 Cb0 0 0 1 Y0 2 Cr0 1 2 Y1 4 Cb2 2 2 5 Y2 6 Cr2 3 7 Y3
1996 Oct 02
14
Bit allocation map
Table 4 DATA BYTE D7 0 0 WSS7 WSSON 0 0 0 0 CBENB OVLY07 OVLU07 OVLV07 OVLY77 OVLU77 OVLV77 CHPS7 GAINU7 GAINV7 GAINU8 GAINV8 CCRS1 0 DOWNB RTCE FSC07 0 DOWNA BSTA6 FSC06 CCRS0 DECTYP 0 GAINV6 GAINV5 BLCKL5 BLNNL5 BLNVB5 0 INPI BSTA5 FSC05 GAINU6 GAINU5 CHPS6 CHPS5 OVLV76 OVLV75 OVLV74 CHPS4 GAINU4 GAINV4 BLCKL4 BLNNL4 BLNVB4 0 YGS BSTA4 FSC04 OVLU76 OVLU75 OVLU74 OVLY76 OVLY75 OVLY74 OVLY73 OVLU73 OVLV73 CHPS3 GAINU3 GAINV3 BLCKL3 BLNNL3 BLNVB3 0 SECAM BSTA3 FSC03 OVLY72 OVLU72 OVLV72 CHPS2 GAINU2 GAINV2 BLCKL2 BLNNL2 BLNVB2 0 SCBW BSTA2 FSC02 OVLY71 OVLU71 OVLV71 CHPS1 GAINU1 GAINV1 BLCKL1 BLNNL1 BLNVB1 0 PAL BSTA1 FSC01 OVLY70 OVLU70 OVLV70 CHPS0 GAINU0 GAINV0 BLCKL0 BLNNL0 BLNVB0 0 FISE BSTA0 FSC00 OVLV06 OVLV05 OVLV04 OVLV03 OVLU06 OVLU05 OVLU04 OVLU03 OVLY06 OVLY05 OVLY04 OVLY03 DISKEY PCREF SYMP DEMOFF FMT16 OVLY02 OVLU02 OVLV02 0 0 GCD4 GCD3 GCD2 0 0 GY4 GY3 GY2 0 0 0 0 0 0 GY1 GCD1 Y2C OVLY01 OVLU01 OVLV01 0 GY0 GCD0 UV2C OVLY00 OVLU00 OVLV00 0 0 0 0 0 0 0 WSS13 WSS12 WSS11 WSS10 WSS9 WSS6 WSS5 WSS4 WSS3 WSS2 WSS1 WSS0 WSS8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D6 D5 D4 D3 D2 D1 D0
1996 Oct 02
Slave receiver (slave address 88H or 8CH)
REGISTER FUNCTION
SUB ADDRESS
Philips Semiconductors
Null
00
Null
25
Wide screen signal
26
Wide screen signal
27
Null
28
Null
37
Gain Y for RGB
38
Gain CD for RGB
39
Input port control
3A
OVL LUT Y0
42
Digital Video Encoder (EURO-DENC2)
15
OVL LUT U0
43
OVL LUT V0
44
OVL LUT Y7
57
OVL LUT U7
58
OVL_LUT_V7
59
Chrominance phase
5A
Gain U
5B
Gain V
5C
Gain U MSB, black level
5D
Gain V MSB, blanking level, decoder type
5E
CCR, blanking level VBI
5F
Null
60
Standard control
61
SAA7182A; SAA7183A
Burst amplitude
62
Preliminary specification
Subcarrier 0
63
DATA BYTE D7 FSC15 FSC23 FSC31 L21O07 L21O17 L21E07 L21E17 SRCV11 HTRIG7 HTRIG10 SBLBN CCEN1 RCV2S7 RCV2E7 0 TTXHS7 TTXHE7 0 TTXOVS7 TTXOVE7 TTXEVS7 TTXEVE7 FAL7 LAL7 0 0 LINE15 LINE23 LINE14 LINE22 0 LAL8 LAL6 LAL5 0 0 LINE13 LINE21 FAL6 FAL5 TTXEVE6 TTXEVE5 TTXEVS6 TTXEVS5 TTXOVE6 TTXOVE5 TTXOVE4 TTXEVS4 TTXEVE4 FAL4 LAL4 FAL8 0 LINE12 LINE20 TTXOVS6 TTXOVS5 TTXOVS4 TTXHE10 TTXHE9 TTXHE8 TTXHE6 TTXHE5 TTXHE4 0 TTXOVS3 TTXOVE3 TTXEVS3 TTXEVE3 FAL3 LAL3 TTXEVE8 0 LINE11 LINE19 TTXHS6 TTXHS5 TTXHS4 TTXHS3 TTXHE3 RCV2E10 RCV2E9 RCV2E8 0 RCV2E6 RCV2E5 RCV2E4 RCV2E3 RCV2S6 RCV2S5 RCV2S4 RCV2S3 RCV2S2 RCV2E2 RCV2S10 TTXHS2 TTXHE2 TTXHS10 TTXOVS2 TTXOVE2 TTXEVS2 TTXEVE2 FAL2 LAL2 TTXOVE8 0 LINE10 LINE18 CCEN0 TTXEN CCLN4 CCLN3 CCLN2 0 PHRES1 PHRES0 0 0 HTRIG9 HTRIG8 VTRIG4 VTRIG3 VTRIG2 HTRIG6 HTRIG5 HTRIG4 HTRIG3 HTRIG2 HTRIG1 VTRIG1 FLC1 CCLN1 RCV2S1 RCV2E1 RCV2S9 TTXHS1 TTXHE1 TTXHS9 TTXOVS1 TTXOVE1 TTXEVS1 TTXEVE1 FAL1 LAL1 TTXEVS8 0 LINE9 LINE17 SRCV10 TRCV2 ORCV1 PRCV1 CBLF ORCV2 L21E16 L21E15 L21E14 L21E13 L21E12 L21E11 L21E06 L21E05 L21E04 L21E03 L21E02 L21E01 L21O16 L21O15 L21O14 L21O13 L21O12 L21O11 L21O10 L21E00 L21E10 PRCV2 HTRIG0 VTRIG0 FLCO CCLN0 RCV2S0 RCV2E0 RCV2S8 TTXHS0 TTXHE0 TTXHS8 TTXOVS0 TTXOVE0 TTXEVS0 TTXEVE0 FAL0 LAL0 TTXOVS8 0 LINE8 LINE16 L21O06 L21O05 L21O04 L21O03 L21O02 L21O01 L21O00 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16 FSC14 FSC13 FSC12 FSC11 FSC10 FSC09 FSC08 D6 D5 D4 D3 D2 D1 D0
REGISTER FUNCTION
SUB ADDRESS
1996 Oct 02
Subcarrier 1
64
Subcarrier 2
65
Subcarrier 3
66
Philips Semiconductors
Line 21 odd 0
67
Line 21 odd 1
68
Line 21 even 0
69
Line 21 even 1
6A
RCV port control
6B
Trigger control
6C
Trigger control
6D
Multi control
6E
Closed caption/teletext control
6F
RCV2 output start
70
RCV2 output end
71
Digital Video Encoder (EURO-DENC2)
16
MSBs RCV2 output
72
TTX request H start
73
TTX request H end
74
MSBs TTX request H
75
TTX odd request V S
76
TTX odd request V E
77
TTX even request V S
78
TTX even request V E
79
First active line
7A
Last active line
7B
MSB vertical
7C
Null
7D
Disable TTX line
7E
SAA7182A; SAA7183A
Preliminary specification
Disable TTX line
7F
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
I2C-bus format Table 5 S Table 6 I2C-bus address; see Table 6 SLAVE ADDRESS ACK SUBADDRESS ACK DATA 0 ACK
SAA7182A; SAA7183A
--------
DATA n
ACK
P
Explanation of Table 5 PART DESCRIPTION START condition 1 0 0 0 1 0 0 X or 1 0 0 0 1 1 0 X (note 1) acknowledge, generated by the slave subaddress byte data byte continued data bytes and ACKs STOP condition
S Slave address ACK Subaddress (note 2) DATA -------P Notes
1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read, no subaddressing with read. 2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed. Slave Receiver Table 7 Subaddress 26 and 27 LOGIC LEVEL - Wide Screen Signalling bits 3 to 0 = aspect ratio 7 to 4 = enhanced services 10 to 8 = subtitles 13 to 11 = reserved WSSON 0 1 Table 8 Subaddress 38 and 39 DESCRIPTION Gain luminance of RGB (Cr, Y and Cb) output, ranging from (1 - 1632) to (1 + 1532). Suggested nominal value = -6 (11010b), depending on external application. Gain Colour Difference of RGB (Cr, Y and Cb) output, ranging from (1 - 1632) to (1 + 1532). Suggested nominal value = -6 (11010b), depending on external application. wide screen signalling output is disabled wide screen signalling output is enabled DESCRIPTION
DATA BYTE WSS0 to WSS13
DATA BYTE GY0 to GY4 GCD0 to GCD4
1996 Oct 02
17
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
Table 9 DATA BYTE UV2C Y2C FMT16 DEMOFF SYMP PCREF DISKEY CBENB Subaddress 3A LOGIC LEVEL 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Cb, Cr data are two's complement. Cb, Cr data are straight binary. Default after reset. Y data is two's complement. Y data is straight binary. Default after reset. DESCRIPTION
SAA7182A; SAA7183A
Selects Cb, Y, Cr and Y on 8 lines on MP port ("CCIR 656" compatible). Default after reset. Selects Cb and Cr on DP port and Y on MP port. Y, Cb and Cr for RGB dematrix is active. Default after reset. Y, Cb and Cr for RGB dematrix is bypassed. Horizontal and vertical trigger is taken from RCV2 and RCV1 respectively. Default after reset. Horizontal and vertical trigger is decoded out of "CCIR 656" compatible data at MP port. Normal polarity of CREF for DIG-TV2 compatible input signals. Inverted polarity of CREF for DIG-TV2 compatible input signals. OVL keying enabled for Y, C and CVBS outputs. Default after reset. OVL keying disabled for Y, C and CVBS outputs. Data from input ports is encoded. Default after reset. Colour bar with programmable colours (entries of OVL_LUTs) is encoded. The LUTs are read in upward order from index 0 to index 7.
1996 Oct 02
18
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
Table 10 Subaddress 42 to 59 DATA BYTE(1) COLOUR OVLY White Yellow Cyan Green Magenta Red Blue Black 107 (6BH) 107 (6BH) 82 (52H) 34 (22H) 42 (2AH) 03 (03H) 17 (11H) 240 (F0H) 234 (EAH) 212 (D4H) 209 (D1H) 193 (C1H) 169 (A9H) 163 (A3H) 144 (90H) 144 (90H) Notes OVLU 0 (00H) 0 (00H) 144 (90H) 172 (ACH) 38 (26H) 29 (1DH) 182 (B6H) 200 (C8H) 74 (4AH) 56 (38H) 218 (DAH) 227 (E3H) 112 (70H) 84 (54H) 0 (00H) 0 (00H)
SAA7182A; SAA7183A
INDEX(2) OVLV 0 (00H) 0 (00H) 18 (12H) 14 (0EH) 144 (90H) 172 (ACH) 162 (A2H) 185 (B9H) 94 (5EH) 71 (47H) 112 (70H) 84 (54H) 238 (EEH) 242 (F2H) 0 (00H) 0 (00H) 7 6 5 4 3 2 1 0
1. Contents of OVL look-up tables. All 8 entries are 8-bits. Data representation is in accordance with "CCIR 601" (Y, Cb and Cr), but two's complement, e.g. for a 100100 (upper number) or 10075 (lower number) colour bar. 2. For normal colour bar with CBENB = logic 1. Table 11 Subaddress 5A DATA BYTE(1) CHPS VALUE tbf tbf tbf tbf Note 1. Phase of encoded colour subcarrier (including burst) relative to horizontal sync. Can be adjusted in steps of 360/256 degrees. RESULT PAL-B/G and data from input ports PAL-B/G and data from look-up table NTSC-M and data from input ports NTSC-M and data from look-up table
1996 Oct 02
19
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
Table 12 Subaddress 5B and 5D DATA BYTE GAINU DESCRIPTION CONDITIONS
SAA7182A; SAA7183A
REMARKS output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal
variable gain for Cb signal; white-to-black = 92.5 IRE(1) input representation GAINU = 0 accordance with GAINU = 118 (76H) "CCIR 601" white-to-black = 100 IRE(2) GAINU = 0 GAINU = 125 (7DH) nominal GAINU for SECAM encoding value = 106 (6AH)
Notes 1. GAINU = -2.17 x nominal to +2.16 x nominal. 2. GAINU = -2.05 x nominal to +2.04 x nominal. Table 13 Subaddress 5C and 5E DATA BYTE GAINV DESCRIPTION variable gain for Cr signal; input representation accordance with "CCIR 601" CONDITIONS white-to-black = 92.5 IRE(1) GAINV = 0 GAINV = 165 (A5H) white-to-black = 100 GAINV = 0 GAINV = 175 (AFH) nominal GAINV for SECAM encoding Notes 1. GAINV = -1.55 x nominal to +1.55 x nominal. 2. GAINV = -1.46 x nominal to +1.46 x nominal. Table 14 Subaddress 5D DATA BYTE BLCKL DESCRIPTION CONDITIONS IRE(1) output black level = 24 IRE output black level = 49 IRE output black level = 24 IRE output black level = 50 IRE REMARKS value = -129 (17FH) IRE(2) output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal REMARKS
variable black level; input white-to-sync = 140 representation accordance BLCKL = 0 with "CCIR 601" BLCKL = 63 (3FH) white-to-sync = 143 BLCKL = 0 BLCKL = 63 (3FH)
IRE(2)
Notes 1. Output black level/IRE = BLCKL x 25/63 + 24; recommended value: BLCKL = 60 (3CH) normal. 2. Output black level/IRE = BLCKL x 26/63 + 24; recommended value: BLCKL = 45 (2DH) normal.
1996 Oct 02
20
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
Table 15 Subaddress 5E DATA BYTE BLNNL DESCRIPTION variable blanking level CONDITIONS white-to-sync = 140 IRE(1) BLNNL = 0 BLNNL = 63 (3FH) white-to-sync = 143 BLNNL = 0 BLNNL = 63 (3FH) DECTYP RTCI logic 0 logic 1 Notes IRE(2)
SAA7182A; SAA7183A
REMARKS output blanking level = 17 IRE output blanking level = 42 IRE output blanking level = 17 IRE output blanking level = 43 IRE real time control input from SAA7151B real time control input from SAA7111
1. Output black level/IRE = BLNNL x 25/63 + 17; recommended value: BLNNL = 58 (3AH) normal. 2. Output black level/IRE = BLNNL x 26/63 + 17; recommended value: BLNNL = 63 (3FH) normal. Table 16 Subaddress 5F DATA BYTE BLNVB CCRS DESCRIPTION variable blanking level during vertical blanking interval is typically identical to value of BLNNL select cross colour reduction filter in luminance; see Table 17
Table 17 Logic levels and function of CCRS CCRS1 0 0 1 1 CCRS0 0 1 0 1 FUNCTION no cross colour reduction; for overall transfer characteristic of luminance see Fig.7 cross colour reduction #1 active; for overall transfer characteristic see Fig.7 cross colour reduction #2 active; for overall transfer characteristic see Fig.7 cross colour reduction #3 active; for overall transfer characteristic see Fig.7
1996 Oct 02
21
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
Table 18 Subaddress 61: DATA BYTE FISE PAL SCBW LOGIC LEVEL 0 1 0 1 0 858 total pixel clocks per line
SAA7182A; SAA7183A
DESCRIPTION 864 total pixel clocks per line; default after reset NTSC encoding (non-alternating V component) PAL encoding (alternating V component); default after reset enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 5 and 6); wide clipping for SECAM standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 5 and 6); default after reset no SECAM encoding; default after reset SECAM encoding activated luminance gain for white - black 100 IRE; default after reset luminance gain for white - black 92.5 IRE including 7.5 IRE set-up of black PAL switch phase is nominal; default after reset PAL switch phase is inverted compared to nominal DACs for CVBS, Y and C in normal operational mode; default after reset DACs for CVBS, Y and C forced to lowest output voltage DACs for R, G and B in normal operational mode; default after reset DACs for R, G and B forced to lowest output voltage
1 SECAM YGS INPI DOWNA DOWNB 0 1 0 1 0 1 0 1 0 1
1996 Oct 02
22
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
Table 19 Subaddress 62A DATA BYTE RTCE LOGIC LEVEL 0 1
SAA7182A; SAA7183A
DESCRIPTION no real time control of generated subcarrier frequency real time control of generated subcarrier frequency through SAA7151B or SAA7111 (timing see Fig.18)
Table 20 Subaddress 62B DATA BYTE BSTA DESCRIPTION amplitude of colour burst; input representation in accordance with "CCIR 601" CONDITIONS white-to-black = 92.5 IRE; burst = 40 IRE; NTSC encoding BSTA = 0 to 1.25 x nominal(1) white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding BSTA = 0 to 1.76 x nominal(2) white-to-black = 100 IRE; burst = 43 IRE; NTSC encoding BSTA = 0 to 1.20 x nominal(3) white-to-black = 100 IRE; burst = 43 IRE; PAL encoding BSTA = 0 to 1.67 x nominal(4) fixed burst amplitude with SECAM encoding Notes 1. Recommended value: BSTA = 102 (66H). 2. Recommended value: BSTA = 72 (48H). 3. Recommended value: BSTA = 106 (6AH). 4. Recommended value: BSTA = 75 (4BH). Table 21 Subaddress 63 to 66 (four bytes to program subcarrier frequency) DATA BYTE DESCRIPTION CONDITIONS f fsc 32 FSC = round ------- x 2 f llc see note 1 REMARKS FSC3 = most significant byte FSC0 = least significant byte REMARKS
FSC0 to FSC3 ffsc = subcarrier frequency (in multiples of line frequency); fllc = clock frequency (in multiples of line frequency) Note 1. Examples:
a) NTSC-M: ffsc = 227.5, fllc = 1716 FSC = 569408543 (21F07C1FH). b) PAL-B/G: ffsc = 283.7516, fllc = 1728 FSC = 705268427 (2A098ACBH). c) SECAM: ffsc = 274.304, fllc = 1728 FSC = 681786290 (28A33BB2H).
1996 Oct 02
23
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
Table 22 Subaddress 67 to 6A DATA BYTE(1) L21O0 L21O1 L21E0 L21E1 Note first byte of captioning data, odd field second byte of captioning data, odd field first byte of extended data, even field second byte of extended data, even field DESCRIPTION
SAA7182A; SAA7183A
1. LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes have to carry the parity bit, in accordance with the definition of Line 21 encoding format. Table 23 Subaddress 6B DATA BYTE PRCV2 LOGIC LEVEL 0 1 ORCV2 CBLF 0 1 0 DESCRIPTION polarity of RCV2 as output is active HIGH, rising edge is taken when input, respectively; default after reset polarity of RCV2 as output is active LOW, falling edge is taken when input, respectively pin RCV2 is switched to input; default after reset pin RCV2 is switched to output if ORCV2 = HIGH, pin RCV2 provides an HREF signal (Horizontal Reference pulse that is defined by RCV2S and RCV2E, also during vertical blanking Interval); default after reset if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal synchronization only (if TRCV2 = 1); default after reset 1 if ORCV2 = HIGH, pin RCV2 provides a `Composite-Blanking-Not' signal, this is a reference pulse that is defined by RCV2S and RCV2E, excluding Vertical Blanking Interval, which is defined by FAL and LAL if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal synchronization (if TRCV2 = 1) and as an internal blanking signal PRCV1 0 1 ORCV1 TRCV2 0 1 0 1 SRCV1 - polarity of RCV1 as output is active HIGH, rising edge is taken when input; default after reset polarity of RCV1 as output is active LOW, falling edge is taken when input pin RCV1 is switched to input; default after reset pin RCV1 is switched to output horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from decoded frame sync of CCIR 656 input (at bit SYMP = HIGH); default after reset horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW) defines signal type on pin RCV1; see Table 24
1996 Oct 02
24
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
Table 24 Logic levels and function of SRCV1 DATA BYTE AS OUTPUT SRCV11 0 0 1 SRCV10 0 1 0 VS FS FSEQ VS FS FSEQ AS INPUT
SAA7182A; SAA7183A
FUNCTION vertical sync each field; default after reset frame sync (odd/even) field sequence, vertical sync every fourth field (PAL = 0), eighth field (PAL = 1) or twelfth field (SECAM = 1) -
1
1
not applicable
not applicable
Table 25 Subaddress 6C and 6D DATA BYTE HTRIG DESCRIPTION sets the horizontal trigger phase related to signal on RCV1 or RCV2 input values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed increasing HTRIG decreases delays of all internally generated timing signals reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV used for triggering at HTRIG = tbf (tbf) Table 26 Subaddress 6D DATA BYTE VTRIG LOGIC LEVEL - DESCRIPTION sets the vertical trigger phase related to signal on RCV1 input increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines variation range of VTRIG = 0 to 31 (1FH) Table 27 Subaddress 6E DATA BYTE SBLBN PHRES FLC LOGIC LEVEL 0 1 - - DESCRIPTION vertical blanking is defined by programming of FAL and LAL; default after reset vertical blanking is forced in accordance with "CCIR 624" (50 Hz) or RS170A (60 Hz) selects the phase reset mode of the colour subcarrier generator; see Table 28 field length control; see Table 29
Table 28 Logic levels and function of PHRES DATA BYTE FUNCTION PHRES1 0 0 1 1 PHRES0 0 1 0 1 no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset reset every two lines or SECAM-specific if bit SECAM = 1 reset every eight fields reset every four fields
1996 Oct 02
25
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
Table 29 Logic levels and function of FLC DATA BYTE
SAA7182A; SAA7183A
FUNCTION FLC1 0 0 1 1 FLC0 0 1 0 1 interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
Table 30 Subaddress 6F DATA BYTE CCEN TTXEN SCCLN LOGIC LEVEL - 0 1 - disables teletext insertion enables teletext insertion selects the actual line, where closed caption or extended data are encoded line = (SCCLN + 4) for M-systems line = (SCCLN + 1) for other systems Table 31 Logic levels and function of CCEN DATA BYTE FUNCTION CCEN1 0 0 1 1 CCEN0 0 1 0 1 Line 21 encoding off enables encoding in field 1 (odd) enables encoding in field 2 (even) enables encoding in both fields DESCRIPTION enables individual Line 21 encoding; see Table 31
Table 32 Subaddress 70 to 72 DATA BYTE RCV2S start of output signal on RCV2 pin values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed first active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at RCV2S = tbfH (tbfH) RCV2E end of output signal on RCV2 pin values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed last active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at RCV2E = tbfH (tbfH) DESCRIPTION
1996 Oct 02
26
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
Table 33 Subaddress 73 to 75 DATA BYTE TTXHS TTXHE DESCRIPTION start of signal on pin TTXRQ (standard for 50 Hz field rate = tbf)
SAA7182A; SAA7183A
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed end of signal on pin TTXRQ (standard for 50 Hz field rate = TTXHS + 1402) values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed Table 34 Subaddress 76, 77 and 7C DATA BYTE TTXOVS TTXOVE DESCRIPTION first line of occurrence of signal on pin TTXRQ in odd field = TTXOVS + 1 (50 Hz field rate) last line of occurrence of signal on pin TTXRQ in odd field = TTXOVE (50 Hz field rate)
Table 35 Subaddress 78, 79 and 7C DATA BYTE TTXEVS TTXEVE DESCRIPTION first line of occurrence of signal on pin TTXRQ in even field = TTXEVS + 1 (50 Hz field rate) last line of occurrence of signal on pin TTXRQ in even field = TTXEVE (50 Hz field rate)
Table 36 Subaddress 7A to 7C DATA BYTE FAL LAL DESCRIPTION first active line = FAL + 4 for M-systems, = FAL + 1 for other systems, measured in lines FAL = 0 coincides with the first field synchronization pulse last active line = LAL + 3 for M-systems, = LAL for other system, measured in lines LAL = 0 coincides with the first field synchronization pulse Table 37 Subaddress 7A to 7C DATA BYTE LINE DESCRIPTION individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective bits, disabled line = LINExx (50 Hz field rate) this bit mask is effective only, if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE SUBADDRESSES In subaddresses 5B, 5C, 5D, 5E and 62 all IRE values are rounded up.
1996 Oct 02
27
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
Slave Transmitter Table 38 Slave transmitter (slave address 89H or 8DH) REGISTER FUNCTION Status byte
SAA7182A; SAA7183A
DATA BYTE SUBADDRESS D7 - VER2 D6 VER1 D5 VER0 D4 D3 D2 0 D1 FSEQ D0 O_E CCRDO CCRDE
Table 39 No subaddress DATA BYTE VER CCRDO LOGIC LEVEL - 1 0 CCRDE 1 0 FSEQ 1 0 O_E 1 0 DESCRIPTION Version identification of the device. It will be changed with all versions of the IC that have different programming models. Current Version is 001 binary. Closed caption bytes of the odd field have been encoded. The bit is reset after information has been written to the subaddresses 67 and 68. It is set immediately after the data has been encoded. Closed caption bytes of the even field have been encoded. The bit is reset after information has been written to the subaddresses 69 and 6A. It is set immediately after the data has been encoded. During first field of a sequence (repetition rate: NTSC = 4 fields, PAL = 8 fields, SECAM = 12 fields. Not first field of a sequence. During even field. During odd field.
1996 Oct 02
28
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
handbook, full pagewidth 6
MBE737
Gv
(dB)
0 -6
-12 -18 -24
(1) (2)
-30 -36 -42 -48 -54 0 (1) SCBW = 1. (2) SCBW = 0. 2 4 6 8 10 12 f (MHz) 14
Fig.5 Chrominance transfer characteristic 1.
handbook, halfpage
2
MBE735
Gv (dB) 0
(1)
(2)
-2
-4
-6
0
0.4
0.8
1.2 f (MHz) 1.6
(1) SCBW = 1. (2) SCBW = 0.
Fig.6 Chrominance transfer characteristic 2.
1996 Oct 02
29
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Gv handbook, full pagewidth (dB) 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 0 2 4 6 8 10 12 f (MHz) 14
(4) (2) (3) (1)
6
MGD672
(1) (2) (3) (4)
CCRS1 = 0; CCRS0 = 1. CCRS1 = 1; CCRS0 = 0. CCRS1 = 1; CCRS0 = 1. CCRS1 = 0; CCRS0 = 0.
Fig.7 Luminance transfer characteristic 1.
handbook, halfpage
MBE736
1
Gv (dB) 0
(1)
-1 -2
-3 -4 -5
0
2
4
f (MHz)
6
(1) CCRS1 = 0; CCRS0 = 0.
Fig.8 Luminance transfer characteristic 2.
1996 Oct 02
30
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
handbook, full pagewidth
Gv 6 0 -6 -12 -18 -24 -30 -36 -42 -48 -54
MGB708
(dB)
0
2
4
6
8
10
12
f (MHz)
14
Fig.9 Luminance transfer characteristic in RGB.
handbook, full pagewidth
Gv 6 0 -6 -12 -18 -24 -30 -36 -42 -48 -54
MGB706
(dB)
0
2
4
6
8
10
12
f (MHz)
14
Fig.10 Colour difference transfer characteristic in RGB.
1996 Oct 02
31
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
handbook, full pagewidth
MGB705
10
Gv (dB) 8
6
4
2
0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 f (MHz) 1.6
Fig.11 Gain of SECAM pre-emphasis.
handbook,30 pagewidth full
MGB704
(deg)
20
10
0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 f (MHz) 1.6
Fig.12 Phase of SECAM pre-emphasis.
1996 Oct 02
32
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
handbook, full pagewidth
MGB703
20
Gv (dB) 16
12
8
4
0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 f (MHz) 1.6
Fig.13 Gain of SECAM anti-Cloche.
handbook, full pagewidth
MGB702
80
(deg) 60
40
20
0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 f (MHz) 1.6
Fig.14 Phase of SECAM anti-Cloche.
1996 Oct 02
33
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
CHARACTERISTICS VDDD(3) = 3.0 to 3.6 V; VDDD(5) = 4.75 to 5.25 V; Tamb = 0 to +70 C; unless otherwise specified. SYMBOL Supply VDDA(3) VDDD(3) VDDD(5) IDDA IDDD(3) IDDD(5) Inputs VIL VIH LOW level input voltage (except SDA, SCL, AP, SP and XTALI) HIGH level input voltage (except LLC, SDA, SCL, AP, SP and XTALI) HIGH level input voltage (LLC) ILI Ci input leakage current input capacitance clocks data Outputs VOL VOH LOW level output voltage (except SDA and XTALO) HIGH level output voltage (except LLC, SDA, and XTALO) HIGH level output voltage (LLC) I2C-bus; SDA and SCL VIL VIH Ii VOL Io TLLC tr tf tSU;DAT tHD;DAT 1996 Oct 02 LOW level input voltage HIGH level input voltage input current LOW level output voltage (SDA) output current Vi = LOW or HIGH IOL = 3 mA during acknowledge -0.5 3.0 -10 - 3 +1.5 +10 0.4 - V A V mA VDDD(5) + 0.5 V note 2 note 2 note 2 0 2.4 2.6 0.6 V -0.5 2.0 2.4 - - - +0.8 V analog supply voltage (3.3 V) digital supply voltage (3.3 V) digital supply voltage (5 V) analog supply current digital supply current (3.3 V) digital supply current (5 V) note 1 note 1 note 1 3.1 3.0 4.75 - - - 3.5 3.6 5.25 110 80 10 V V V mA mA mA PARAMETER CONDITIONS MIN. MAX. UNIT
VDDD(5) + 0.5 V VDDD(5) + 0.5 V 1 10 8 8 A pF pF pF
I/Os at high impedance -
VDDD(5) + 0.5 V VDDD(5) + 0.5 V
Clock timing (LLC) cycle time duty factor tHIGH/TLLC rise time fall time note 3 note 4 note 3 note 3 34 40 - - 41 60 5 6 - - ns % ns ns
Input timing input data set-up time (any other except CDIR, SCL, SDA, RESET, AP and SP) input data hold time (any other except CDIR, SCL, SDA, RESET, AP and SP) 34 6 3 ns ns
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
SYMBOL Crystal oscillator fn f/fn Tamb CL RS C1 C0 CL th td Vo(p-p) Rint RL B ILE DLE Notes
PARAMETER
CONDITIONS -
MIN.
MAX.
UNIT
nominal frequency (usually 27 MHz) permissible deviation of nominal frequency
3rd harmonic note 5
30 +50
MHz 10-6 C pF fF pF
-50 0 8 -
CRYSTAL SPECIFICATION operating ambient temperature load capacitance series resistance motional capacitance (typical) parallel capacitance (typical) 70 - 80
1.5 -20% 1.5 +20% 3.5 -20% 3.5 +20%
Data and reference signal output timing output load capacitance output hold time output delay time 7.5 4 - 40 - 25 pF ns ns
CHROMA, Y, CVBS and RGB outputs output signal voltage (peak-to-peak value) internal serial resistance output load resistance output signal bandwidth of DACs LF integral linearity error of DACs LF differential linearity error of DACs -3 dB note 6 1.35 1 75 10 - - 1.45 3 300 - 2 1 V MHz LSB LSB
1. At maximum supply voltage with highly active input signals. 2. The levels have to be measured with load circuits of 1.2 k to 3.0 V (standard TTL load) and CL = 25 pF. 3. The data is for both input and output direction. 4. With LLC in input mode. In output mode, with a crystal connected to XTALO/XTALI duty factor is typically 50%. 5. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. 6. For full digital range, without load, VDDA = 3.3 V. The typical voltage swing is 1.4 V, the typical minimum output voltage (digital zero at DAC) is 0.2 V.
1996 Oct 02
35
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
handbook, full pagewidth
tHIGH
TLLC 2.6 V 1.5 V 0.6 V
LLC clock output tHD; DAT tHIGH LLC clock input tf TLLC tr
2.4 V 1.5 V 0.8 V tSU; DAT tHD; DAT tf tr 2.0 V
input data
valid td
not valid
valid 0.8 V
tHD; DAT output data valid
2.4 V not valid valid 0.6 V
MBE742
Fig.15 Clock data timing.
handbook, full pagewidth
LLC
MP(n)
Cb(0)
Y(0)
Cr(0)
Y(1)
Cb(2)
RCV2
MGB699
The data demultiplexing phase is coupled to the internal horizontal phase. The phase of the RCV2 signal is programmed to tbf (tbf for 50 Hz) in this example in output mode (RCV2S).
Fig.16 Functional timing.
1996 Oct 02
36
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
handbook, full pagewidth
LLC
CREF
MP(n)
Y(0)
Y(1)
Y(2)
Y(3)
Y(4)
DP(n)
Cb(0)
Cr(0)
Cb(2)
Cr(2)
Cb(4)
RCV2
MBE739
The data demultiplexing phase is coupled to the internal horizontal phase. The CREF signal applies only for the 16 line digital TV format, because these signals are only valid in 13.5 MHz. The phase of the RCV2 signal is programmed to tbf (tbf for 50 Hz) in this example in output mode (RCV2S).
Fig.17 Digital TV timing.
handbook, full pagewidth
H/L transition count start LOW 128
13
4 bits reserved HPLL increment
0 21
sequence reserved (2) 5 bits bit (1) reset reserved bit (3) FSCPLL increment (4)
0
RTCI time slot: 0 1
14 19 67 68
not used in SAA7182A/83A
valid sample
invalid sample
8/LLC
MGD673
(1) Sequence bit: PAL = logic 0 then (R - Y) line normal; PAL = logic 1 then (R - Y) line inverted. NTSC = logic 0 then no change. (2) Reserved bits: 235 with 50 Hz systems; 232 with 60 Hz systems. (3) Only from SAA7111 decoder. (4) SAAA7111 provides (22 : 0) bits, resulting in 3 reserved bits before sequence bit.
Fig.18 RTCI timing.
1996 Oct 02
37
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
Teletext timing Time tFD is the time needed to interpolate input data TTX and inserting it into the CVBS and Y output signal, such that it appears at tTTX = 10.2 s after the leading edge of the horizontal synchronization pulse. Time tPD is the pipeline delay time introduced by the source that is gated by TTXRQ in order to deliver TTX data. Since the pulse representing the TTXRQ signal is fully programmable in duration and rising/falling edges (TTXHS and TTXHE), the TTX data is always inserted at the correct position of 10.2 s after the leading edge of outgoing horizontal synchronization pulse. Time tTTXWin is the internally used insertion window for TTX data; it has a constant length that allows insertion of 360 teletext bits (maximum) at a text data rate of 6.9375 Mbits/s. The insertion window is not opened if the control bit TTXEN is zero. TELETEXT PROTOCOL The frequency relationship between TTX bit clock and the system clock LLC for 50 Hz field rate is given by the relationship of line frequency multiples, which means 1728/444.
SAA7182A; SAA7183A
Thus 37 TTX bits correspond to 144 LLC clocks, each bit has a duration of nearly 4 LLC clocks. The chip-internal sequencer and variable phase interpolation filter minimizes the phase jitter, and thus generates a bandwidth limited signal, which is digital-to-analog converted for the CVBS and Y outputs. At the TTX input, bit duration scheme repeats after 37 TTX bits or 144 LLC clocks. The protocol demands that TXX bits 10, 19, 28 and 37 are carried by three LLC samples, all others by four LLC samples. After a cycle of 37 TTX bits, the next bits with three LLC samples are bits 47, 56, 65 and 74; this scheme holds for all succeeding cycles of 37 TTX bits, until 360 TTX bits (including 16 run-in bits) are completed. For every additional line with TTX data, the bit duration scheme starts in the same way. Using appropriate programming, all suitable lines of the odd field (TTXOVS and TTXOVE) plus all suitable lines of the even field (TTXEVS and TTXEVE) can be used for teletext insertion.
handbook, full pagewidth
CVBS/Y tTTX textbit #: TTX 4 tPD tFD 3 4 1/LLC 4 3 4 1/LLC 1 2 3 4 5 6 7 8 9 10 11 12 tTTXWin 13 14 15 16 17 18 19 20 21 22 23 24
TTXRQ
MGB701
Fig.19 Teletext timing diagram.
1996 Oct 02
38
+3.3 V analog 100 nF VSSA 100 nF 100 nF VSSA 100 nF VSSA 100 nF 100 nF VSSA VSSA 100 nF VSSA VDDA5 VDDA4 VDDA3 VDDA2 VDDA1 64 RED 2 (1) 61 75 VSSA GREEN 2 (1) 58 75 27 GREEN 0.7 V (p-p)(2)(4) VSSA BLUE 2 (1) 55 27 75 BLUE 0.7 V (p-p)(2)(4) VSSA 2 (1) 73 8 75 CVBS 1.23 V (p-p)(2) VSSA 2 (1) 71 13 75 Y 1.0 V (p-p)(2) VSSA 2 (1) 69 13 75 62 QI 59 BI 56 65 SELI 52, 67, 76 VSSA1 to VSSA3 RI CHROMA 0.62 V (p-p)(2) VSSA
MGD674
VSSD 3.3 V oscillator VSSD VSSD 100 nF VSSA 100 nF 100 nF VDDD6 46 27 RED 0.7 V (p-p)(2)(4) 74 72 70 68 63 60 57 54 VDDA9 VDDA8 VDDA7 VDDA6 VSSA VSSA
SAA7182A; SAA7183A
Preliminary specification
Fig.20 Application environment of the EURO-DENC2; PLCC84.
handbook, full pagewidth
1996 Oct 02
42
10 H
10 pF
Philips Semiconductors
1 nF
X1 27.0 MHz (3)
10 pF
3rd harmonic
XTALI
XTALO VSSD6
APPLICATION INFORMATION
44
45
digital inputs and outputs
VSSD
100 nF V DDD2 14
Digital Video Encoder (EURO-DENC2)
VSSD
100 nF V DDD4 29
39
SAA7182A SAA7183A
VSSD
100 nF V DDD7 49
VSSD
100 nF V DDD9 82
+5 V digital
VSSD
100 nF V DDD1 5
VSSD
100 nF V DDD3 22
VSSD
100 nF V DDD5 38
VSSD
100 nF V DDD8 80
3, 15, 24, 30, 39, 51, 79, 81
+3.3 V digital
VSSD1 to VSSD5 and VSSD7 to VSSD9
(1) Typical value. (2) For 100100 colour bar. (3) Philips 12NC ordering code: 9922 520 30003. (4) Depending on GY/GCD value.
+3.3 V analog 100 nF VSSA 100 nF 100 nF VSSA 100 nF VSSA 100 nF 100 nF VSSA VSSA 100 nF VSSA VDDA5 VDDA4 VDDA3 VDDA2 VDDA1 53 RED 2 50 75
(1)
SAA7182A; SAA7183A
Preliminary specification
Fig.21 Application environment of the EURO-DENC2; QFP80.
handbook, full pagewidth
1996 Oct 02
3.3 V oscillator VSSD 100 nF VSSA 100 nF 100 nF VDDD6 34 27 RED 0.7 V (p-p)(2)(4) VSSA GREEN 2 (1) 47 27 75 GREEN 0.7 V (p-p)(2)(4) VSSA BLUE 2 (1) 44 27 75 BLUE 0.7 V (p-p)(2)(4) VSSA 2 (1) 61 8 75 CVBS 1.23 V (p-p)(2) VSSA 2 (1) 59 13 75 Y 1.0 V (p-p)(2) VSSA 2 (1) 57 13 75 51 RI 48 QI 45 BI 54 SELI 41, 55, 64 VSSA1 to VSSA3 CHROMA 0.62 V (p-p)(2) VSSA
MGD707
VSSD
10 H
10 pF
Philips Semiconductors
1 nF VSSA
X1 27.0 MHz (3)
10 pF
VSSD
VSSA
3rd harmonic VDDA9 VDDA8 VDDA7 VDDA6 62 60 58 56 52 49 46 43
XTALI 31
XTALO VSSD6
32
33
digital inputs and outputs
VSSD
100 nF V DDD2 5
Digital Video Encoder (EURO-DENC2)
VSSD
100 nF V DDD4 19
40
SAA7182A SAA7183A
VSSD
100 nF V DDD7 37
VSSD
100 nF V DDD9 70
+5 V digital
VSSD
100 nF V DDD1 13
VSSD
100 nF V DDD3 28
VSSD
100 nF V DDD5 68
VSSD
100 nF V DDD8 76
6, 14, 20, 29, 39, 67, 69, 74
+3.3 V digital
VSSD1 to VSSD5 and VSSD7 to VSSD9
(1) Typical value. (2) For 100100 colour bar. (3) Philips 12NC ordering code: 9922 520 30003. (4) Depending on GY/GCD value.
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
Analog output voltages The analog output voltages are dependent on the open loop voltage of the operational amplifiers for full-scale conversion (typical value 1.4 V), the internal series resistor (typical value 2 ), the external series resistor and the external load impedance. The digital output signals in front of the DACs under nominal conditions occupy different conversion ranges, as indicated in Table 40 for a 100100 colour bar signal. Table 40 Digital output signals conversion range CONVERSION RANGE (peak-to-peak CVBS, SYNC TIP-TO-PEAK CARRIER (digits) 1023 Y (VBS) SYNC TIP-TO-WHITE (digits) 888
SAA7182A; SAA7183A
Values for the external series resistors result from a 75 load (see Figs 20 and 21). The analog inputs RI, GI, and BI are shifted first by an offset of 0.16 V (typical value), followed by an amplification of 1.72 (typical value). For an input voltage of 0 to 0.7 V an open loop output voltage of 0.28 to 1.48 V is achieved, resulting in Vo = 0.86 V (p-p) with an internal series resistor of 2 , an external series resistor of 27 at a 75 load impedance.
RGB (Y) BLACK-TO-WHITE AT GDY = GDC = -6 (digits) 712
1996 Oct 02
41
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
PACKAGE OUTLINES PLCC84: plastic leaded chip carrier; 84 leads
SAA7182A; SAA7183A
SOT189-2
eD y 74 75 X 54 53 Z E A
eE
bp b1 wM 84 HE A A4 A1 (A 3) k1 Lp detail X 12 e D HD 0 5 scale DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT
mm inches
1
pin 1 index e
E
k
11 32 ZD
33
vM A B vMB 10 mm
A
4.57 4.19
A1 min.
0.51
A3
0.25
A4 max.
3.30 0.13
bp
0.53 0.33
b1
0.81 0.66
D (1)
E (1)
e
eD
eE
HD
HE
k
k1 max.
0.51
Lp
1.44 1.02
v
0.18
w
0.18
y
0.10
Z D(1) Z E (1) max. max.
2.16 2.16
29.41 29.41 28.70 28.70 30.35 30.35 1.22 1.27 29.21 29.21 27.69 27.69 30.10 30.10 1.07
45 o
0.180 0.020 0.01 0.165
1.130 1.130 1.195 1.195 0.048 0.057 0.021 0.032 1.158 1.158 0.020 0.05 0.007 0.007 0.004 0.085 0.085 1.090 1.090 1.185 1.185 0.042 0.040 0.013 0.026 1.150 1.150
Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION SOT189-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-03-11
1996 Oct 02
42
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT318-2
c
y X
64 65
41 40 ZE
A
e E HE wM pin 1 index bp 25 1 wM D HD ZD B vM B 24 vMA A A2 A1
Q (A 3) Lp L detail X
80
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.2 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.45 0.30 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.8 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 Q 1.4 1.2 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.0 0.6 1.2 0.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT318-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-12-15 95-02-04
1996 Oct 02
43
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all PLCC and QFP packages. The choice of heating method may be influenced by larger PLCC or QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering PLCC Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow.
SAA7182A; SAA7183A
* The package footprint must incorporate solder thieves at the downstream corners. QFP Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). METHOD (PLCC AND QFP) During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Oct 02
44
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7182A; SAA7183A
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 Oct 02
45

▲Up To Search▲

Price & Availability of SAA7182AWP

	To Download SAA7182AWP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .